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Digital Vision Àü¹®±â¾÷ ASIC /FPGA Engineer
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ASIC/FPGA Engineer
- VHDL.
- Verilog.
- Synopsys: Design Compiler, Prime Time.
- Cadence: Apollo II.
- Model Technology: ModelSim.
- Synthesis and some layout.
- Xilinx FPGAs (Virtex II and Virtex II Pro) and ISE.
- C++, including STL.
- CMOS standard cell synthesis, simultation and verification.
- DFT.
- JTAG.
- UNIX, Linux and Windows 2000 OS.
- SRAM, DRAM and Flash usage and interfacing.
- PLL and DLL usage.
- High-speed and LVDS signaling.
Á÷±Þ: ÆÀÀå±Þ.
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³ªÀÌ:30~40¼¼.
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±¹¹® À̷¼, ÀÚ±â¼Ò°³¼(Èñ¸Á±Þ¿© ¸í½Ã, MS-Word ÀÛ¼º). Email: top@topheadhunter.co.kr·Î ¼ÛºÎ.
¸ðÁý±â°£:ASAP.
Our Contact: (ÁÖ)žÇìµåÇåÅÍ ÇìµåÇåÆà Á¦1ÆÀ ÆÀÀå
Contact Person:Man-Shik Seo
Title: CEO
Tel No.: 82-2-555-7310
Fax No.: 82-2-561-1441
Mobile No.: 016-441-1442
E-mail:ceo@topheadhunter.co.kr
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